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Defines |
| #define | MODNAME "pci32: " |
| #define | MODID PCDSP_MODID_PCI32 |
| #define | PCI_VENDOR_ID_INNOVATIVE 0x10e8 |
| #define | PCI_DEVICE_ID_PCI32DSP 0x807c |
| #define | PCI32_BASE pcdsp_iobase |
| #define | PCI32_CTRL PCI32_BASE+0x00 |
| #define | PCI32_IRQ0 PCI32_BASE+0x04 |
| #define | PCI32_IRQ1 PCI32_BASE+0x08 |
| #define | PCI32_SEMANZ 4 |
| #define | PCDSP_SEMANZ PCI32_SEMANZ |
| #define | PCI32_SEM0 0x0C |
| #define | PCI32_SEM1 0x10 |
| #define | PCI32_SEM2 0x14 |
| #define | PCI32_SEM3 0x18 |
| #define | GET_SEM(N) outw(1, pcdsp_iobase+pci32_sems[N]) |
| #define | FREE_SEM(N) outw(0, pcdsp_iobase+pci32_sems[N]) |
| #define | SEM(N) (inw(pcdsp_iobase+pci32_sems[N])&1) |
| #define | CLR_IRQ0 outw(0, PCI32_IRQ0) |
| #define | SET_IRQ0 outw(1, PCI32_IRQ0) |
| #define | CLR_IRQ1 outw(0, PCI32_IRQ1) |
| #define | SET_IRQ1 outw(1, PCI32_IRQ1) |
| #define | PCDSP_HALT_X outw(1, PCI32_CTRL) |
| #define | PCDSP_RUN_X outw(0, PCI32_CTRL) |
Variables |
| static unsigned long | pci32_sems [4] = { PCI32_SEM0, PCI32_SEM1, PCI32_SEM2, PCI32_SEM3 } |